1. Field of the Invention
The present invention relates to a distortion compensating device and more particularly to a distortion compensating device applicable to a high frequency power amplifier and a power amplifying device with a distortion compensating function.
2. Description of the Related Art
Generally speaking, in a mobile telephone employing a CDMA (Code Division Multiple Access) system, the transmission power of a terminal is constantly fluctuating and the peak of output distribution is in the vicinity of about 10 mW in the case where voice is used. Therefore, in many of the CDMA mobile telephone terminals, the power-supply voltage of a power amplifier (PA) is changed between low output and high output by using a DC-DC converter to increase efficiency in the low output. However, as the mobile telephone terminal becomes to include more data processing functions, it is considered that the transmission power distribution is shifting to the higher output side.
Consequently, the output of as high a power as possible particularly in a state of a low power-supply voltage leads to low power consumption in the entire terminal. More specifically, it is important to make higher a switching power threshold at which switching between the low output and the high output is performed. However, when the switching power threshold is made higher, distortion is increased, so that reducing the distortion in the low output is an important issue. Although distortion compensation techniques have been proposed since some years ago, they cannot be immediately applied to the mobile telephone terminal in view of an increase in circuit scale or the like.
In recent years, there has been proposed a technique in which the distortion is improved by injecting a second harmonic (Non-patent Documents 1 to 4).
FIG. 2 shows a typical device configuration closest to the present invention. In FIG. 2, an input signal is divided into two in a dividing circuit (div) 21 and one of the divided signals is inputted to a gate of a small-size gate grounded FET (Field Effect Transistor) 22. A second harmonic generated in the FET 22 is extracted in a band pass filter (BPF) 23. Thereafter, for the extracted second harmonic, a phase and amplitude thereof are adjusted by a phase shift circuit (Ph) 24 and an attenuation circuit (ATT) 25 respectively to input them in a first input terminal of an addition circuit (add) 26. On the other hand, the other output of the dividing circuit 21 is inputted to a second input terminal of this addition circuit 26 and this addition output is inputted to an input terminal of a power amplifier (A) 27. Distortion generated by the power amplifier 27 is reduced by optimally adjusting the phase and the amplitude of the second harmonic generated in the FET 22 by the phase shift circuit 24 and the attenuation circuit 25, respectively.
[Non-Patent Document 1]
    K. Joshin, Y. Nakasha, T. Iwai, T. Miyashita, S. Ohara, “Harmonic Feedback Circuit Effects on Intermodulation Products and Adjacent Channel Leakage Power in HBT Power Amplifier for 1.9 GHz Wide-Band CDMA Cellular Phones,” IEICE Trans. Electron., vol. E82-C, No. 5, May, 1999, pp. 725-729.[Non-Patent Document 2]    M. R. Moazzam, C. S. Aitchison, “A Low Order Intermodulation Amplifier with Harmonic Feedback Circuitry, “IEEEMTT-S Digest, 1996, WE3F-5.[Non-Patent Document 3]    D. Jing, W. Chan S. M. Li, C. S. Li, “New Linearization Method Using Interstage Second Harmonic Enhancement,” IEEE Microwave and Guide Wave Letters, vol. 8, No. 11, pp. 402-404, Nov. 1998.[Non-Patent Document 4]    N. Males-Ilic, B. Milovanovic, D. Budimir, “Low Intermodulation Amplifiers for RF and Microwave Wireless System, “Asian Pacific Microwave Conference 2001, Proceedings pp. 984-987.[Non-Patent Document 5]    S. Kusunoki, T. Furuta and Y. Murakami, “An analysis of higher-order IMD depending on source impedance of a GaAs FET and its application to a design of low distortion MMIC power amplifiers, “Electronics and Communications in Japan, vol. 85, No. 4, pp. 10-21, Apr. 2002, John Wiley and Sons, Inc. NY. USA. (“An analysis of higher-order intermodulation distortion depending on gate connected impedance and improvement in digital modulation distortion of power amplifiers,” Japanese Journal of The Institute of Electronics, Information and Communication Engineers, vol. J83-C, No. 6, pp. 542-552, June 2000.)
An amount of the phase to be rotated by the phase shift circuit 24 included in the configuration of FIG. 2 is determined according to a nonlinear characteristic of the power amplifier 27 subjected to the distortion compensation. The phase shift circuit 24 is composed of a delay line such as a strip line. Since the circuit scale depends on a frequency and the frequency of CDMA commercialized at present in Japan is a 900 MHz band, there is a drawback that the scale becomes relatively large.